Tiny GPU FPGA Port — Sipeed Tang Nano 20K

Project Overview

This is the FPGA arm of the 32-Bit Tiny GPU project: taking a design that was written for simulation and an ASIC flow, and making it fit and run on a real, small, cheap FPGA. The target is a Sipeed Tang Nano 20K — a Gowin GW2AR-18C QN88 with a 27 MHz onboard oscillator. That board has far fewer LUTs, registers and routing resources than the simulation configuration assumes, so the port is not a recompile. The design drops from 4 cores × 4 threads executing in parallel to a single core with a single thread executing four blocks sequentially, which trades throughput for fit while keeping the programming model and the ISA identical. Around the GPU core sits a hardware top level that does the things a testbench used to do for free: bring up the clock, initialise program and data memory from hex images, drive a launch FSM to start execution, light status LEDs, and stream results back over UART so the board can be observed without a debugger. The port is a separate concern from the ASIC flow — the same RTL also goes through OpenLane to a signoff-clean GDSII on SkyWater 130 nm.